Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As the geometry limits of the structures used to form semiconductor devices are pushed against technology limits, the need to form structures having small critical dimensions and high aspect ratios with different materials has become increasingly difficult to achieve. Chemical mechanical planarization, or chemical mechanical polishing (CMP) is a common technique which is useful in removing undesired surface topography, or in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even or level surface for subsequent deposition and processing. During a CMP process, relative motion is provided between the substrate and polishing surface of a polishing pad to planarize the surface of the substrate in contact with the pad through one or a combination of a chemical, mechanical, or electrochemical process. However, mechanical abrasion during the CMP process may also result in undesired micro-scratches, dishing, residuals or other undesired defects on the structures of the substrate.
There is, therefore, a need to solve the issues associated with the above deficiencies.